1. Field of the Invention
The present invention relates to a processing unit, such as a digital signal processor (hereafter called “DSP”), which can perform a same computing processing for a plurality of independent identical data by a common program with relatively small power consumption, when the processing unit is used in stereo-voice processing, for example.
2. Description of the Related Art
Advanced digital processing often includes digital processing of voice data and image data. Various processing units have been proposed to execute product sum computation that is frequently used for the digital processing of voice data and image data at high speed. One of such processing units is, for example, a DSP disclosed in Japanese Patent Kokai (Laid-Open Application) No. H5-35774 and Japanese Patent Kokai (Laid-Open Application) No. 2000-293357. This DSP includes a data computing unit for executing computing processing, such as product sum computation, and a control unit for generating various control signals to control the data computing unit.
FIG. 4(1) and FIG. 4(2) of the accompanying drawings are block diagrams depicting the above mentioned conventional DSP 5, disclosed in Japanese Patent Applications Kokai No. H5-35774 and No. 2000-293357. FIG. 4(1) shows the data computing unit 10 of the DSP 5, and FIG. 4(2) shows the control unit 20 of the DSP 5.
The data computing unit 10 includes a coefficient read only memory (hereafter called “coefficient ROM”) 11 for storing the coefficient data of a product sum computation, and a C pointer 12 for indicating the coefficient data read position in the coefficient ROM 11. The data computing unit 10 also includes a data random access memory (hereafter called “data RAM”) 13 of which writing is controlled by the write control signal WR1, for storing the variable data of a product sum computation, and a D pointer 14 for indicating the read position of the variable data in the data RAM 13. The data computing unit 10 also includes a multiplier 15. The multiplier 15 is connected to the output terminal of the coefficient ROM 11 and the output terminal of the data RAM 13. The multiplier 15 is a circuit for performing the multiplication of the coefficient data and the variable data.
The data computing unit 10 also includes a selector 16, an arithmetic and logic unit (hereinafter referred to as “ALU”) 17, and a register 18. The first input terminal of the ALU 17 is connected to the output terminal of the multiplier 15. The output terminal of the selector 16 is connected to the second input terminal of the ALU 17. The selector 16 is a circuit for selecting one of the input data IN and the output data OUT. The input terminal of the register 18 is connected to the output terminal of the ALU 17. The register 18, of which writing is controlled by the write control signals WR2, is a circuit for holding the output data of the ALU 17. The output terminal of the register 18 is connected to the input terminal of the data RAM 13 and the input terminal of the selector 16.
The control unit 20 has a selector 21. A program counter (hereafter “PC”) 22, a program ROM 23 and an instruction decoder 24 are sequentially connected to the output terminal of the selector 21. The selector 21 is a circuit for selecting either the signals when the output data of the PC 22 is incremented +1 by the control signal provided by the instruction decoder 24, or control signals, such as a jump (JUMP) instruction, provided by the instruction decoder 24. The PC 22 is a circuit for counting based on the clock CK, and generating the address for a reading instruction to the program ROM 23. The program ROM 23 is a memory for storing a program comprised of a plurality of instructions and reading an instruction in the program specified by the address that is supplied from the PC 22. The instruction decoder 24 is a circuit for decoding the instruction read from the program ROM 23, and producing various control signals to execute the instruction (e.g., control signals of the C pointer 12, control signals of the D pointer 14, write control signals WR1 and WR2, output switching signals of the selector 16, control signals of the multiplier 15, control signals of the ALU 17, control signals of the PC 22, control signals of the program ROM 23 and control signals of the JUMP instruction).
In the DSP 5 having such a configuration, the product sum computation of the expression (A), which is frequently used in digital processing, is implemented by the following (1)-(7). Expression (A) is the continuation of expression (B).Y=Σai×xi   (A)Ci+1=Ci+(ai×xi)   (B)
(1) The coefficient data ai of the address indicated by the C pointer 12 is supplied from the coefficient ROM 11 to the multiplier 15.
(2) The variable data xi of the address indicated by the D pointer 14 is supplied from the data RAM 13 to the multiplier 15.
(3) The coefficient data ai and the variable data xi are multiplied in the multiplier 15.
(4) The data sent from the register 18 via the selector 16 and the output data of the multiplier 15 are added in the ALU 17.
(5) The output data of the ALU 17 is stored in the register 18.
(6) The value of the C pointer 12 is changed to the address of the next coefficient data.
(7) The value of the D pointer 14 is changed to the address of the next variable data.
These processings (1)-(7) are executed within one cycle. Accordingly, a product sum computation frequently used in digital processing can be executed at high-speed.
The conventional DSP 5, however, has the following problems (a) and (b).
(a) For example, when a same computing processing is performed on two independent data (right channel data R-ch and left channel data L-ch) in stereo-voice processing, generally the right channel data R-ch is processed, and then the left channel data L-ch is processed. In this case, each pointer 12 and 14 operates twice (right channel and left channel processing) respectively, and these unnecessary pointer operations generate unnecessary power consumption. This increases a total power consumption.
(b) For example, if the right channel and the left channel data of stereo-voice data are regarded as monaural data, the program developed for monaural data cannot be used, and a new program must be developed for stereo-voice processing even though the same computing processing is performed for the data. This is inconvenient.